Mac ethernet hub full#
Mac ethernet hub code#
Mac ethernet hub mac#

Mac ethernet hub code#

How does this work? This code fragment only takes effect when the control header is being presented on the bus. Note 1: `IOQ_DST_PORT_POS is a Macro that decodes to the value 48. emacs ~/.bashrc &Ĭhange this line: export NF_DESIGN_DIR=$ bashrc file to point to your new ethernet_hub project instead of the old reference_nic project. More details on using Subversion will be provided in a future tutorial.Ĭhange the environment variable in your. Tip: Normally, this would be a good time to check this project into Subversion, but this is not necessary for this tutorial. Then, enter your new projects directory and copy the reference_nic project, which will be the foundation of your new design.

Mac ethernet hub full#

To create the Ethernet Hub, first start by copying the full NetFPGA directory into your own home directory: cp -R /exports/provided/netfpga/ ~/. To begin, start your X server, enable X11 tunneling, and SSH to.

Odd numbered ports CPU (DMA) ports - Numbered 1, 3, 5, 7.

Mac ethernet hub mac#

Even-numbered ports are Ethernet MAC ports - Numbered 0, 2, 4, 6.

These ports have a specific numbering scheme:

CPU (DMA) ports corresponding to the IO sources/sinks - 4.

In the NetFPGA design, there are 8 possible input (RX) ports and 8 possible output (TX) ports. You can use a macro to select this bit range: `IOQ_SRC_PORT_POS+15:`IOQ_SRC_PORT_POS Input port (binary encoding, not one-hot encoding) IOQ Packet Header (added by RX Queue) Control Value The format of the header is placed at the beginning of every received packet is: This behavior is enabled by default from nf2_core.v, which also gives each MAC port a unique queue number. The four MAC RX Queues (one for each Ethernet port) defined in $NF_ROOT/lib/verilog/io_queues/ethernet_mac/src/rx_queue.v each can optionally add a control header at the beginning of every packet received. Similarly, a control value of 0x04 (0b00000100) indicates that there are six bytes in the final word, and the last byte is stored in bits 23:16. Remember, bytes are stored in the most significant byte position first. For example, a control value of x40 (0b01000000) at the end of a packet indicates that there are two bytes in the last word, and the last data byte is stored in bits 55:47.

Note 3: To determine where the last byte of packet data is, examine the control value closely. Note 2: The last word of packet data can always be detected by testing for a non-zero control value. bits 63-56), and so on until the data is finished. Note 1: The first byte of the packet is stored in the most significant byte position (byte 7, i.e. Packet data - Last word (bit vector indicates indicates position of last byte) Packet data (Ethernet header / IP header / Payload) - Word 2 Packet data (Ethernet header / IP header / Payload) - Word 1 Packet with Control Headers Control Value An example packet with header is shown below: They can also communicate when no packet is available by just sending a header. Modules communicate by appending headers to the beginning of an arriving packet. They can start and stop at any time, even in the middle of a packet. Note that modules are *not* required to push their data forward in one continuous packet-sized burst. Each path is composed of the following signals:Įach module tells the preceding module when it is ready to accept data, and that preceding module pushes data forward and uses the write signal to denote when the data and control buses are currently valid.

There are two data paths where packet data enters and leaves your module: Input (from the preceding module) and Output (to the next module). Before beginning the tutorial, recall from the class lecture that the NetFPGA platform is constructed as a sequence of independent modules, and data flows through these modules as a pipeline.